Stereo Vision IP Core Released

We have released the FPGA-design that drives our SP1 stereo vision sensor as a reusable IP core. This allows our customers to integrate stereo vision functionality into new FPGA-based products.

At the heart of our SP1 stereo vision sensor is an efficient FPGA-based stereo matching implementation. We have implemented a variation of the Semi Global Matching (SGM) stereo algorithm, which provides us with high quality stereo matching results in real-time.

Stereo vision is a very versatile technique. It can be used in many areas such as robotics, inspection, surveillance or human machine interaction. We want to support the development of new stereo-vision-based products and technologies in these and further areas. We therefore release our FPGA design as a reusable IP core.

The stereo vision IP core can be integrated into your own FPGA designs. It performs all necessary processing steps that are required for a stereo vision sensor. This includes image rectification, image pre-processing, stereo matching, and post-processing.

A detailed explanation of all features of the stereo vision core can be found in the stereo vision core data sheet.

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